This invention relates generally to semiconductor processing, and more particularly to the placement of alignment marks for subsequence use in conjunction with such processing.
Semiconductor fabrication is a complex and expensive process. Complicated circuits are designed and fabricated at the sub-micron level, with tens of thousands or more of individual semiconductor transistors. The failure of only a small number of these transistors, however, can render a semiconductor device defective. Instead of relegating such defective devices to scrap, semiconductor manufacturers frequently try to first repair them, to recoup their investment as much as possible. The yield of operative semiconductor devices to the total number of devices fabricated can determine whether a manufacturer is profitable. As the yield increases, the manufacturer""s unit costs decrease.
Repair is especially important in semiconductor memories. A semiconductor memory may have redundant rows or columns that can be logically replaced for rows or columns that have defective memory cells. The replacement is made by precision tools that take wafer probe failure data, locate the failed element, and use a laser to perform microsurgery on links to remove the defective element and connect a replacement in its place. Laser processing for repair of such memories involves complex thermal and mechanical coupled mechanisms. Although carrying spare elements on a die adds cost overhead, yields can be improved through repair by as much as tens of percent, justifying this added overhead.
For laser and other repair of semiconductor memories and other semiconductor devices, masks, and reticles, as well as for other aspects of semiconductor processing, such as lithography and deposition, alignment is important. For instance, if layers are not deposited properly, or if they are not selectively removed properly, the resulting semiconductor devices may not function, relegating them to scrap, which can be costly. Therefore, alignment marks are placed on the semiconductor wafer for the proper positioning during the deposition and photolithography processes. In the context of semiconductor device repair, alignment marks serve to guide the repair process. For instance, a laser may focus on the alignment marks, or otherwise utilize them so that repair is properly accomplished.
In FIG. 1, a semiconductor wafer 102 is shown that has alignment marks, such as the alignment square 104, thereon. When a photomask 106 is positioned over the wafer 102, its own alignment marks, such as the alignment square 108, is aligned with the alignment marks of the wafer 102. For example, the alignment square 108 of the photomask 106 is aligned so that the alignment square 104 of the wafer 102 is centered therein. The alignment marks of the semiconductor wafer 102 are located in the individual dies, or devices, of the wafer 102. This is disadvantageous, because chip area is increased without a corresponding increase in device functionality or storage. Furthermore, where a design has already been finalized for fabrication, which is known as tape out, it is difficult to subsequently add alignment marks within the devices themselves.
In other types of semiconductor processing, alignment marks are placed in two fields, or areas, on opposite edges of the semiconductor wafer. In FIG. 2, a wafer 200 is divided into a number of fields, such as the field 202. Each field corresponds to one or more semiconductor devices, and represents an area of the wafer that will be processed at a given time. For instance, a stepper may first process one field, then move on to the next field, and so on. The wafer 200 has an upper-right field 204 and a lower-left field 206 that have alignment marks 208 and 210, respectively. The presence of the marks 208 and 210 on the fields 204 and 206 presents difficulties with semiconductor processing of these fields, however. The alignment marks 208 and 210 should not be obscured, so that proper alignment for subsequent processing can still occur. The marks 208 and 210 also increase chip area of the individual dies in which they are located.
Another approach to alignment mark placement is to locate the marks within the scribe lines that separate the individual dies on a wafer. In FIG. 3, a semiconductor wafer 302 on which patterns such as alignment marks can be placed is shown. The wafer 302 has a number of semiconductor device areas, such as the areas 304 and 306. Each device area of the wafer 302 is for a separate device to be fabricated. The device areas themselves may also be referred to as chips, dies, devices, circuits, microchips, and bars. They are used to identify the microchip patterns covering the majority of the surface of the wafer 302. Scribe lines, such as the scribe lines 308 and 308, separate the device areas. The scribe lines are also referred to as saw lines, streets, and avenues, and are the spaces between the chips that allow separation of the chip from the wafer.
Locating the alignment marks within the scribe lines does not increase chip area, but unfortunately this approach has other disadvantages. Overlay patterns, photo alignment keys, critical dimension bars, test lines, and other patterns are commonly already included in the scribe lines, limiting where the alignment marks can be placed, since they cannot be placed on these patterns. For semiconductor memories in particular, desirably each die has at least one alignment mark, and preferably has three alignment marks, such that placing the marks in the scribe lines is difficult to accomplish with the other patterns already occupying the lines.
There fore, there is a need for an alignment mark that can be more flexibly placed within semiconductor dies. Such an alignment mark should avoid the location difficulties associated with placing such marks on scribe lines. Such an alignment mark should also desirably not decrease the chip area of a given die. For these and other reasons, there is a need for the present invention.
The invention relates to high contrast alignment mark s that can be flexibly located on a semiconductor wafer. The wafer has a first layer and a second layer. The first layer has a light-dark intensity and a reflectivity. The second layer is over the first layer, and has a light-dark intensity substantially lighter than that of the first layer, and a higher reflectivity than that of the first layer. The first layer may be patterned to further darken it. The second layer contrasts visibly to the first layer, and is patterned to form at least one or more alignment marks within the second layer. The first layer may be a metallization layer, such as titanium nitride, whereas the second layer may be a metallization layer, such as aluminum or copper.
The invention provides for advantages over the prior art. The high reflectivity of the second layer as compared to the low reflectivity of the first layer means that the alignment marks patterned in the second layer have increased visibility. Furthermore, the first and second layers can be added even on top of a die, giving added flexibility in placement of the alignment marks. Three alignment marks may be added per die using the invention, which is the preferred number for semiconductor memories. Chip size does not increase where the alignment marks are added to the top of a die, and the alignment marks may be added even where a die design has already been finalized at tape out. Semiconductor memories employing the invention can be repaired at a high rate, ensuring a high yield.
Still other aspects, embodiments, and advantages of the invention will become apparent by reading the detailed description and by referring to the accompanying drawings.